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1 |
Title of the Programme |
M.Tech. (DECS) |
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2 |
Curricula and Syllabi |
Copy Enclosed |
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3 |
Faculty Profile |
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S.No |
Name |
Designation |
Subject Teaching |
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1 |
R V S Satyanarayana |
Professor |
Detection and
Estimation of Signals |
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2 |
B. Abdul Rahim |
Professor
|
Digital Data
Communication |
|
3 |
K.Sreenivasa Rao |
Asso Professor |
Advanced
digital signal processing |
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Brief profile of each Faculty |
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Laboratory facilities exclusive to the PG program, all
design tools in case |
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Active HDL ( VHDL / veilo & simulation
software ) & simplify Prof ( FPGA syntherns software ) &
Universal FPGA / CPLD designkits. From Tech Labs, Hyd.
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Special Purpose |
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Software, all design tools in case
|
---- |
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Academic Calendar and frame Work |
---- |
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Research focus |
---- |
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List of Typical research projects
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Industry Linkage |
---- |
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Publications (if any) out of research in
last three years out of masters Projects
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Placement status |
---- |
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Admission procedure |
Through GATE and PGECET-2007 as per merit
order |
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Fee Structure |
Rs. 27,575 / - per sem |
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Hostel Facilities |
Available for girls |
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Contact address of co- ordinator of the PG programme
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Name |
B. Abdul Rahim |
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Address |
HOD. Dept. of ECE |
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Telephone
|
9848998644 |
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Note:-
Suppression and/or misrepresentation of information
would attract appropriate penal action. |
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